The present invention relates to a clock frequency divider circuit and, particularly, to a clock frequency divider circuit that divides the frequency of an input clock signal and generates a clock signal with an arbitrary frequency dividing ratio.
Conventionally, each element in a semiconductor integrated circuit is controlled with a clock signal as a basis, and the operating speed of each element is determined by the clock signal. A quartz oscillator is generally used as an oscillating source for generating a clock signal supplied to a semiconductor integrated circuit, because of the stability and accuracy of the quartz oscillator.
Since clock signals of various frequencies are required in a semiconductor integrated circuit, a signal resulting from 1/D (D is a natural number) division of the frequency of a clock signal may be used. Such division of the frequency of a clock signal can be easily performed by using a scale-of-D counter.
On the other hand, as prior art, a clock signal generating circuit is proposed in which a m-bit adder, storing means for storing data preceding by one clock, and a m-bit, D-type flip-flop circuit are used, external input data having a value n is inputted to one input terminal of the adder, and an output of the adder is connected to one input terminal of the D-type flip-flop circuit. In the prior art, a system clock is inputted to another input terminal of the D-type flip-flop circuit, an output of the D-type flip-flop circuit is connected to another input terminal of the adder, and the most significant bit of the output signal of the D-type flip-flop circuit is outputted as a clock signal (see Japanese Patent Laid-open No. 2001-127618(FIG. 1), for example).
Letting n be the value of the external input data and m be the number of bits of the adder and the D-type flip-flop circuit, the frequency dividing ratio DR1 of the clock signal generating circuit isDR1=2m/n(where 2m>n)